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Cypress Semiconductor /psoc63 /BLE /BLESS /ENC_PARAMS

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Interpret as ENC_PARAMS

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0DATA_PDU_HEADER 0PAYLOAD_LENGTH_LSB 0 (DIRECTION)DIRECTION 0PAYLOAD_LENGTH_LSB_EXT 0 (MEM_LATENCY_HIDE)MEM_LATENCY_HIDE

Description

Encryption Parameter register

Fields

DATA_PDU_HEADER

LLID of the packet.
PAYLOAD_LENGTH_LSB

Length of the input data.
DIRECTION

The directionBit shall be set to ‘1’ for Data Channel PDUs sent by the master and set to ‘0’ for Data Channel PDUs sent by the slave.
PAYLOAD_LENGTH_LSB_EXT

3 Most significant bits of the LS byte of the length of the input data. Valid only when DLE is enabled. When DLE is enabled total ENC payload length = {PAYLOAD_LENGTH_LSB_EXT, PAYLOAD_LENGTH_LSB}
MEM_LATENCY_HIDE

Controls the encryption memory access mode. Valid only when DLE is enabled. 0 - The AES is idle while memory fetch/store in progress. 1- The AES is pipelined while memory fetch/store in progress.

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Register License

Copyright 2016-2018 Cypress Semiconductor Corporation \n Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License.
You may obtain a copy of the License at \n
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and
limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data